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ics for communications two channel codec filter with iom ? -2 interface (iom ? -2 C sicofi ? -2) peb 2265 version 1.1 preliminary data sheet 1997-07-01 t2265-xv11-p1-7600
edition 1997-07-01 hl ts, balanstra?e 73, 81541 mnchen ? siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. peb 2265 revision history: current version: 1997-07-01 previous version: page (in previous version) page (in current version) subjects (major changes since last revision)
peb 2265 table of contents page semiconductor group 3 1997-07-01 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3 pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3.1 common pins for all channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3.2 specific pins for channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.3.3 specific pins for channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2iom ? -2 C sicofi ? -2 principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1 iom ? -2 C sicofi ? -2 signal flow graph (for either channel) . . . . . . . . . .12 2.1.1 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1.2 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1.3 loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1.4 test features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2 iom ? -2 C sicofi ? -2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3.1 iom ? -2 interface timing for 16 voice channels (per 8 khz frame) . . . . . .15 2.3.2 iom ? -2 interface timing (dcl = 4096 khz, mode = 1, per 8 khz frame) 15 2.3.3 iom ? -2 interface timing (dcl = 2048 khz, mode = 0) . . . . . . . . . . . . . .16 2.3.4 iom ? -2 time-slot selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3 programming the iom ? -2 C sicofi ? -2 . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1 types of monitor bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.2 iom ? -2 C sicofi ? -2 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.2.1 sop - write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.2.2 xop - write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.2.3 cop - write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.2.4 sop - read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.2.5 xop - read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.2.6 cop - read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.2.7 example for a mixed command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.3 sop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.3.1 cr1 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.3.2 cr2 configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.3 cr3 configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.4 cr4 configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4 cop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.5 xop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.5.1 xr1 extended register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.5.2 xr2 extended register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.5.3 xr3 extended register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.4 xr4 extended register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.6 slic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
peb 2265 table of contents page semiconductor group 4 1997-07-01 3.7 iom ? -2 interface command/indication byte . . . . . . . . . . . . . . . . . . . . . . .38 3.8 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.8.1 reset (basic setting mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.8.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.8.3 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.9 programmable filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.9.1 impedance matching filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.9.2 transhybrid balancing (th) filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.9.3 filters for frequency response correction . . . . . . . . . . . . . . . . . . . . . . . .43 3.9.4 amplification/attenuation -filters ax1, ax2, ar1, ar2 . . . . . . . . . . . . . .44 3.9.5 amplification/attenuation receive (ar1, ar2)-filter . . . . . . . . . . . . . . . .44 3.9.6 amplification/attenuation transmit (ax1, ax2)-filter . . . . . . . . . . . . . . . .44 4 qsicos software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.1 qsicos supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5 transmission characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.1 frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.1.1 receive: reference frequency 1 khz, input signal level 0 dbm0 . . . . . . . .48 5.1.2 transmit: reference frequency 1 khz, input signal level 0 dbm0 . . . . . . .48 5.2 group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.2.1 group delay absolute values: input signal level 0 dbm0 . . . . . . . . . . . . .49 5.2.2 group delay distortion transmit: input signal level 0 dbm0 . . . . . . . . . . .49 5.2.3 group delay distortion receive: input signal level 0dbm0 . . . . . . . . . . . .50 5.3 out-of-band signals at analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.4 out-of-band signals at analog output . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.5 out of band idle channel noise at analog output . . . . . . . . . . . . . . . . . .52 5.6 overload compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.7 gain tracking (receive or transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.8 total distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.8.1 total distortion measured with sine wave . . . . . . . . . . . . . . . . . . . . . . . .53 5.8.2 total distortion measured with noise according to ccitt . . . . . . . . . . . .54 5.9 single frequency distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 5.10 transhybrid loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 6.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.3 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.4 analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.5 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.6 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.6.1 4 mhz operation mode (mode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.6.2 2 mhz operation mode (mode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
peb 2265 table of contents page semiconductor group 5 1997-07-01 6.7 iom ? -2 command/indication interface timing . . . . . . . . . . . . . . . . . . . . .61 6.7.1 4 mhz operation mode (mode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 6.7.2 2 mhz operation mode (mode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.8 detector select timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 6.8.1 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 7 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7.1 iom ? -2 interface monitor transfer protocol . . . . . . . . . . . . . . . . . . . . . . .64 7.1.1 monitor channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7.1.2 monitor handshake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 7.1.3 state diagram of the iom ? -2 C sicofi ? -2 monitor transmitter . . . . . . . .66 7.1.4 state diagram of the iom ? -2 C sicofi ? -2 monitor receiver . . . . . . . . . .67 7.2 monitor channel data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 7.2.1 address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 7.2.2 identification command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 7.3 iom ? -2 interface programming procedure . . . . . . . . . . . . . . . . . . . . . . . .69 8 test features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.1 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.1.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.1.2 the tap-controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.2 level metering function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 8.3 programming the iom ? -2 C sicofi ? -2 tone generators . . . . . . . . . . . .76 9 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4 m c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , asm ? , asp ? are trademarks of siemens ag. purchase of siemens i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c-system provided the system conforms to the i 2 c specifications defined by philips. copyright philips 1983.
peb 2265 overview semiconductor group 6 1997-07-01 1 overview the two channel codec filter peb 2265 iom-2 C sicofi-2 is the logic continuation of a well-established family of siemens codec-filter-ics. the iom-2 C sicofi-2 is a fully integrated pcm codec and filter fabricated in low power 1 m m cmos technology for applications in digital communication systems. based on an advanced digital filter concept, the peb 2265 provides excellent transmission performance and high flexibility. the new filter concept (second generation) lends to a maximum of independence between the different filter blocks. each filter block can be seen like an one to one representative of the corresponding network element. only very few external components are needed, to complete the functio nality of the iom-2 C sicofi-2. the internal level accuracy is based on a very accurate bandgap reference. the frequency behavior is mainly determined by digital filters, which do not have any fluctuations. as a result of the new adc and dac concepts linearity is only limited by second order parasitic effects. although the device works with only one single 5-v supply there is a very good dynamic range available.
p-mqfp-64-1-2 semiconductor group 7 1997-07-01 two channel codec filter with iom ? -2 interface iom ? -2 C sicofi ? -2 peb 2265 type ordering code package peb 2265 h v1.1 on request p-mqfp-64-1-2 1.1 features ? single chip codec and filter to handle two co- or pabx-channels ? specification according to relevant ccitt, eia and lssgr recommendations ? digital signal processing technique ? programmable interface optimized to current feed slics and transformer solutions ? four pin serial iom-2 interface ? single power supply 5 v ? advanced low power 1 m m analog cmos technology ? standard 64-pin p-mqfp-64 package ? high performance analog to digital conversion ? high performance digital to analog conversion ? programmable digital filters to adapt the transmission behavior especially for C ac impedance matching C transhybrid balancing C frequency response C gain ? advanced test capabilities C all digital pins can be tested within a boundary scan scheme (ieee 1149.1) C five digital loops C four analog loops C two programmable tone generators per channel ? comprehensive development platform available C software for automatic filter coefficient calculation C qsicos C hardware development board C stut 2465
peb 2265 overview semiconductor group 8 1997-07-01 1.2 pin configuration (top view) figure 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.u.io. n.u.io. n.u.io. n.u.io. n.u.i. n.u.i. n.u.i. n.u.i. n.u.i. n.u.i. n.c. iom2-sicofi-2 n.c.
peb 2265 overview semiconductor group 9 1997-07-01 1.3 pin definition and functions 1.3.1 common pins for all channels table 1 pin no. symbol input (i) output (o) function 23 vddd i + 5 v supply for the digital circuitry 1) 58 gndd i ground digital, not internally connected to gnda 1, 2 or gnda (pin 6 and pin 11). all digital signals are referred to this pin 40 vdda12 i + 5 v analog supply voltage for channel 1 and 2 1) 9 vdda i + 5 v analog supply voltage 1) 6,11 gnda i ground analog, not internally connected to gndd or gnda1,2 27 fsc i iom-2: frame synchronization clock, 8 khz 26 dcl i iom-2: data clock, 2048 khz or 4096 khz depending on mode 25 du o iom-2: data upstream, open drain output 24 dd i iom-2: data downstream, input 22 reset i reset input - forces the device to the default mode, active high 57 mode i iom-2: mode selection 60 tss0 i iom-2: time slot selection pin 0 59 tss1 i iom-2: time slot selection pin 1 56 tck i boundary scan: test clock 55 tms i boundary scan: test mode select 54 tdi i boundary scan: test data input 53 tdo o boundary scan: test data output 28 lgkm0 o loop/ground key mul tiplexing o utput 0 for channel 1, 2 41 vh12 i/o reference voltage for channel 1 and 2, has to be connected via a 220 nf cap. to ground 18,19,20 61,62,63 n.u.i. i none usable input, tie directly to digital ground
peb 2265 overview semiconductor group 10 1997-07-01 1.3.2 specific pins for channel 1 1) a 100 nf cap. should be used for blocking these pin. 1,16 17,64 n.u.io. i/o none usable input/output, tie via a pull-down-resistor to digital ground 2,3,4,5,7 8,10,12 13,14,15 21 n.c. not connected table 2 pin no. symbol input (i) output (o) function 38 gnda1 i ground analog for channel 1, not internally connected to gndd or gnda2 or gnda (pin 6 and pin 11) 39 vin1 i analog voice (voltage) input for channel 1 37 vout1 o analog voice (voltage) output for channel 1 31 si1_0 i signaling indication input pin 0 for channel 1 30 si1_1 i signaling indication input pin 1 for channel 1 29 si1_2 i signaling indication input pin 2 for channel 1 36 so1_0 o signaling command output pin 0 for channel 1 35 so1_1 o signaling command output pin 1 for channel 1 34 so1_2 o signaling command output pin 2 for channel 1 33 sb1_0 i/o bi-directional signal. command indication pin 0 for channel 1 32 sb1_1 i/o bi-directional signal. command indication pin 1 for channel 1 table 1 (contd) pin no. symbol input (i) output (o) function
peb 2265 overview semiconductor group 11 1997-07-01 1.3.3 specific pins for channel 2 table 3 pin no. symbol input (i) output (o) function 43 gnda2 i ground analog for channel 2, not internally connected to gndd or gnda1 or gnda (pin 6 and pin 11) 42 vin2 i analog voice (voltage) input for channel 2 44 vout2 o analog voice (voltage) output for channel 2 50 si2_0 i signaling indication input pin 0 for channel 2 51 si2_1 i signaling indication input pin 1 for channel 2 52 si2_2 i signaling indication input pin 2 for channel 2 45 so2_0 o signaling command output pin 0 for channel 2 46 so2_1 o signaling command output pin 1 for channel 2 47 so2_2 o signaling command output pin 2 for channel 2 48 sb2_0 i/o bi-directional signal. command indication pin 0 for channel 2 49 sb2_1 i/o bi-directional signal. command indication pin 1 for channel 2
peb 2265 iom ? -2 C sicofi ? -2 principles semiconductor group 12 1997-07-01 2iom ? -2 C sicofi ? -2 principles the change from 2 m m to 1 m m cmos process requires new concepts in the realization of the analog functions. high performance (in the terms of gain, speed, stability ) 1 m m cmos devices can not withstand more than 5.5 v of supply voltage. on that account the negative supply voltage v ss of the previous sicofis will be omitted. this is a benefit for the user but it makes a very high demand on the analog circuitry. adc and dac are changed to sigma-delta-concepts to fulfill the string ent requirements on the dynamic parameters. using 1 m m cmos does not only lend to problems C it is the only acceptable solution in terms of area and power consumption for the integration of more then two sicofi channels on a single chip. it is rather pointless to implement 2 codec-filter-channels on one chip with pure analog circuitry. the use of a dsp-concept (the sicofi and the sicofi-2-approach) for this function seems to be a must for an adequate two channel architecture. 2.1 iom ? -2 C sicofi ? -2 signal flow graph (for either channel) figure 2
peb 2265 iom ? -2 C sicofi ? -2 principles semiconductor group 13 1997-07-01 2.1.1 transmit path the analog input signal has to be dc-free connected by an external capacitor because there is an internal virtual reference ground potential. after passing a simple antialiasing prefilter (prefi) the voice signal is converted to a 1-bit digital data stream in the sigma-delta-converter. the first downsampling steps are done in fast running digital hardware filters. the following st eps are implemented in the micro-code which has to be executed by the central digital signal processor. this dsp-machine is able to handle the workload for all two channels. at the end the fully processed signal (flexibly programmed in many parameters) is transferred to the iom-2 interface in a pcm-compressed signal representation. 2.1.2 receive path the digital input signal is received via the iom-2 interface. expansion, pcm-law-pass-filtering, gain correction and frequency response correction are the next steps which are done by the dsp-machine. the upsampling interpolation steps are again processed by fast hardware structures to reduce the dsp-workload. the upsampled 1-bit data stream is then converted to an analog equivalent which is smoothed by a post-filter (pofi). as the signal vout is also referenced to an internal virtual ground potential, an external capacitor is required for dc-decoupling. 2.1.3 loops there are two loops implemented. the first is to generate the ac-input impedance (im) and the second is to perform a proper hybrid balancing (th). a simple extra path im2 (from the transmit to the receive path) supports the impedance matching function. 2.1.4 test features there are four analog and five digital test loops implemented in the iom-2 C sicofi-2. for special tests it is possible to cut off the receive and the transmit path at two different points.
peb 2265 iom ? -2 C sicofi ? -2 principles semiconductor group 14 1997-07-01 2.2 iom ? -2 C sicofi ? -2 block diagram figure 3 the iom-2 C sicofi-2 bridges the gap between analog and digital voice signal transmission in modern telecommunication systems. high performance oversampling analog-to-digital converters (adc) and digital-to-analog converters (dac) provide the required conversion accuracy. analog antialiasing prefilters (prefi) and smoothing postfilters (pofi) are included. the connection between the adc and the dac (with high sampling rate) and the dsp, is done by specific hardware filters, for filtering like interpolation and decimation. the dedicated digital signal processor (dsp) handles all the algorithms necessary e.g. for pcm bandpass filtering, sample rate conversion and pcm companding. the iom-2 interface handles digital voice transmission, iom-2 C sicofi-2 feature control and transparent access to the iom-2 C sicofi-2 command and indication pins. to program the filters, precalculated sets of coefficients are downloaded from the system to the on chip coefficient ram (cram). 2.3 iom ? -2 interface the iom-2 interface consists of two data lines and two clock lines. du (data upstream) carries data from the iom-2 C sicofi-2 to a master device. this master device performs the interface between the pcm-backplane, the m controller and up to 24 iom-2 C sicofi-2's. dd (data downstream) carries data from the master device to the iom-2-sicof-2. a frame synchronization clock signal (8 khz, fsc) as well as a data clock signal (2048 khz or 4096 khz dcl) has to be supplied to the iom-2 C sicofi-2. the iom-2 C sicofi-2 handles data as described in the iom-2 specification for analog devices. dsp hw-filter hw-filter iom2-bus signaling iom2-interface signaling dac dac adc adc analog out analog in analog out analog in command indication command indication iom3.wmf
peb 2265 iom ? -2 C sicofi ? -2 principles semiconductor group 15 1997-07-01 2.3.1 iom ? -2 interface timing for 16 voice channels (per 8 khz frame) figure 4 2.3.2 iom ? -2 interface timing (dcl = 4096 khz, mode = 1, per 8 khz frame) figure 5
peb 2265 iom ? -2 C sicofi ? -2 principles semiconductor group 16 1997-07-01 2.3.3 iom ? -2 interface timing (dcl = 2048 khz, mode = 0) figure 6 2.3.4 iom ? -2 time slot selection the two channels (1 and 2) of the iom-2 C sicofi-2 can be assigned to 4 time slots by pin-strapping the pins tss0 and tss1 (ts0, ts2, ts4, ts6). the iom-2 operating mode is selected by the mode pin. table 4 tss1 tss0 mode iom ? -2 operating mode 0 0 1 time slot 0; dcl= 4096 khz 0 1 1 time slot 2; dcl= 4096 khz 1 0 1 time slot 4; dcl= 4096 khz 1 1 1 time slot 6; dcl= 4096 khz 0 0 0 time slot 0; dcl= 2048 khz 0 1 0 time slot 2; dcl= 2048 khz 1 0 0 time slot 4; dcl= 2048 khz 1 1 0 time slot 6; dcl= 2048 khz
peb 2265 iom ? -2 C sicofi ? -2 principles semiconductor group 17 1997-07-01 each iom time slot contains 2 voice channels (a and b). those two voice channels share a common iom-monitor-byte as well as a common c/i-byte. the ad-bit in the monitor command defines which of the two voice channels should be affected (programmed). (for more information on iom-2 specific monitor channel data structure see appendix, page 64 ). figure 7 table 5 tss1 = 0, tss0 = 0 tss1 = 0, tss0 = 1 tss1 = 1, tss0 = 0 tss1 = 1, tss0 = 1 iom ? -2 C sicofi ? -2 channels ts voice channel ts voice channel ts voice channel ts voice channel 1 ts0 a ts2 a ts4 a ts6 a 2 ts0 b ts2 b ts4 b ts6 b
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 18 1997-07-01 3 programming the iom ? -2 C sicofi ? -2 with the appropriate commands, the iom-2 C sicofi-2 can be programmed and verified very flexibly via the iom-2 interface monitor channel. data transfer to the iom-2 C sicofi-2 starts with a sicofi-specific address byte (81 h ). with the second byte one of 3 different types of commands (sop, xop and cop) is selected. each of those can be used as a write or read command. due to the extended iom-2 C sicofi-2 feature control facilities, sop, cop and xop commands contain additional information (e.g. number of subsequent bytes) for programming (write) and verifying (read) the iom-2 C sicofi-2 status. a write command is followed by up to 8 bytes of data. the iom-2 C sicofi-2 responds to a read command with its iom-2 specific address and the requested information, that is up to 8 bytes of data (see programming procedure, page 18 ). attention: each byte on the monitor channel, has to be sent twice at least, according to the iom-2 monitor handshake procedure (for more information on iom-2 specific monitor channel data structure see appendix, page 64 ). 3.1 types of monitor bytes the 8-bit monitor bytes have to be interpreted as either commands or status information stored in configuration registers or the coefficient ram. there are three different types of iom-2 C sicofi-2 commands which are selected by bit 3 and 4 as shown below. sop status operation: iom-2 C sicofi-2 status setting/monitoring xop extended operatio: c/i channel configuration/evaluation cop coefficient operation: filter coefficient setting/monitoring bit76543210 10 bit76543210 x11 bit76543210 0
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 19 1997-07-01 storage of programming information: 4 configuration registers per channel: cr1, cr2, cr3, cr4 accessed by sop commands 4 common configuration registers: xr1, xr2, xr3 and xr4 accessed by xop commands (the contents are valid for two voice channels i.e. 1 iom-2 time slot) 1 coefficient ram per channel: cram accessed by cop commands 3.2 iom ? -2 C sicofi ? -2 commands 3.2.1 sop - write commands dd 76543210bit 76543210 du address 10000001 idle sop-write 1 byte 0 10001 idle cr1 data idle dd 76543210bit 76543210 du address 1 0 000001 idle sop-write 2 bytes 0 10010 idle cr2 data idle cr1 data idle 0 dd 76543210bit 76543210 du address 1 0 000001 idle sop-write 3 bytes 0 10011 idle cr3 data idle cr2 data idle cr1 data idle
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 20 1997-07-01 3.2.2 xop - write commands dd 76543210bit 76543210 du address 10000001 idle sop-write 4 bytes 0 1 0 1 0 0 idle cr4 data idle cr3 data idle cr2 data idle cr1 data idle dd 76543210bit 76543210 du address 10000001 idle xop-write 2 bytes 0 1 1 0 1 0 idle xr2 data idle xr1 data idle dd 76543210bit 76543210 du address 10000001 idle xop-write 3 bytes 0 1 1 0 1 0 idle xr3 data idle xr2 data idle xr1 data idle
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 21 1997-07-01 3.2.3 cop - write commands dd 76543210bit 76543210 du address 1 0 000001 idle cop-write 4 bytes 0 0 1 idle coeff. 4 data idle coeff. 3 data idle coeff. 2 data idle coeff. 1 data idle dd 76543210bit 76543210 du address 1 0 000001 idle cop-write 8 bytes 0 0 0 idle coeff. 8 data idle coeff. 7 data idle coeff. 6 data idle coeff. 5 data idle coeff. 4 data idle coeff. 3 data idle coeff. 2 data idle coeff. 1 data idle
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 22 1997-07-01 3.2.4 sop - read commands dd 76543210bit 76543210 du address 10000001 idle sop-read 1 byte 1 1 0 0 0 1 idle idle 10000001 address idle data cr1 dd 76543210bit 76543210 du address 10000001 idle sop-read 2 bytes 1 1 0 0 1 0 idle idle 10000001 address idle data cr2 idle data cr1 dd 76543210bit 76543210 du address 10000001 idle sop-read 3 bytes 1 1 0 0 1 1 idle idle 10000001 address idle data cr3 idle data cr2 idle data cr1 dd 76543210bit 76543210 du address 10000001 idle sop-read 4 bytes 1 1 0 1 0 0 idle idle 10000001 address idle data cr4 idle data cr3 idle data cr2 idle data cr1
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 23 1997-07-01 3.2.5 xop - read commands dd 76543210bit 76543210 du address 1 0 000001 idle xop-read 1 byte 1 11001 idle idle 10000001ad dress idle data xr1 dd 76543210bit 76543210 du address 1 0 000001 idle xop-read 2 bytes 1 11010 idle idle 10000001ad dress idle data xr2 idle data xr1 dd 76543210bit 76543210 du address 10000001 idle xop-read 3 bytes 1 11011 idle idle 1 0 0 0 0 0 0 1 address idle data xr3 idle data xr2 idle data xr1
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 24 1997-07-01 3.2.6 cop - read commands dd 76543210bit 76543210 du address 10000001 idle cop-read 4 bytes 1 0 1 idle idle 10000001 address idle data coeff.4 idle data coeff.3 idle data coeff.2 idle data coeff.1 dd 76543210bit 76543210 du address 1 0 000001 idle cop-read 8 bytes 1 0 0 idle idle 10000001 address idle data coeff.8 idle data coeff.7 idle data coeff.6 idle data coeff.5 idle data coeff.4 idle data coeff.3 idle data coeff.2 idle data coeff.1
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 25 1997-07-01 3.2.7 example for a mixed command dd 76543210bit 76543210 du address 1 0 000001 idle sop-write 4 bytes 0 10100 idle cr4 data idle cr3 data idle cr2 data idle cr1 data idle xop-write 2 bytes 0 11010 idle xr2 data idle xr1 data idle cop-write 4 bytes 0 0 1 idle coeff. 4 data idle coeff. 3 data idle coeff. 2 data idle coeff. 1 data idle sop-read 3 bytes 1 10011 idle idle 10000001ad dress idle data cr3 idle data cr2 idle data cr1 address 1 0 000001 idle cop-read 4 bytes 1 0 1 idle idle 10000001ad dress idle data coeff.4 idle data coeff.3 idle data coeff.2 idle data coeff.1 address 1 0 000001 idle xop-read 1 byte 1 11001 idle idle 10000001ad dress idle data xr1
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 26 1997-07-01 3.3 sop command to modify or evaluate the iom-2 C sicofi-2iom-2 C sicofi-2 status, the contents of up to four configuration registers cr1, cr2, cr3 and cr4 may be transferred to or from the iom-2 C sicofi-2. this is started by a sop-command (status operation command). ad address information ad = 0 iom-2 C sicofi-2 channel 1 is addressed with this cmd. ad = 1 iom-2 C sicofi-2 channel 2 is addressed with this cmd. rw read/write information: enables reading from the iom-2 C sicofi-2 or writing information to the iom-2 C sicofi-2 rw = 0 write to iom-2 C sicofi-2 rw = 1 read from iom-2 C sicofi-2 pwrup power up / power down pwrup = 1 sets the assigned channel (see bit ad) of iom-2 C sicofi-2 to power-up (operating mode) pwrup = 0 resets the assigned channel of iom-2 C sicofi-2 to power-down (standby mode) lsel length select information (see also programming procedure) this field identifies the number of subsequent data bytes lsel = 000 0 bytes of data are following lsel = 001 1 byte of data is following (cr1) lsel = 010 2 bytes of data are following (cr2, cr1) lsel = 011 3 bytes of data are following (cr3, cr2, cr1) lsel = 100 4 bytes of data are following (cr4, cr3, cr2, cr1) all other codes are reserved for future use! it is possible to program each configuration register separately, just by putting only one byte into the fifo of the upstream master device (e.g. epic), and aborting after transmission of one (or n) byte. bit76543210 ad rw pwrup 1 0 lsel2 lsel1 lsel0
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 27 1997-07-01 3.3.1 cr1 configuration register 1 configuration register cr1 defines the basic iom-2 C sicofi-2 settings, which are: enabling/disabling the programmable digital filters and tone generators. th enable th- (trans hybrid balancing) filter th = 0: th-filter disabled th = 1: th-filter enabled im/r1 enable im-(impedance matching) filter and r1-filter im/r1 = 0: im-filter and r1-filter disabled im/r1 = 1: im-filter and r1-filter enabled frx enable frx (frequency response transmit)-filter frx = 0: frx-filter disabled frx = 1: frx-filter enabled frr enable frr (frequency response receive)-filter frr = 0: frr-filter disabled frr = 1: frr-filter enabled ax enable ax-(amplification/attenuation transmit) filter ax = 0: ax-filter disabled ax = 1: ax-filter enabled ar enable ar-(amplification/attenuation receive) filter ar = 0: ar-filter disabled ar = 1: ar-filter enabled etg2 enable programmable tone generator 2 1) etg2 = 0: programmable tone generator 2 is disabled etg2 = 1: programmable tone generator 2 is enabled etg1 enable programmable tone generator 1 etg1 = 0: programmable tone generator 1 is disabled etg1 = 1: programmable tone generator 1 is enabled 1) tone generator 2 is not available if level metering function is enabled! bit76543210 th im/r1 frx frr ax ar etg2 etg1
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 28 1997-07-01 3.3.2 cr2 configuration register 2 th-sel 2 bit field to select one of two programmed th-filter coefficient sets th-sel = 0 0: th-filter coefficient set 1 is selected th-sel = 0 1: th-filter coefficient set 2 is selected lm level metering function 1) lm = 0: level metering function is disabled lm = 1: level metering function is enabled lmr result of level metering function (this bit can not be written) lmr = 0: level detected was lower than the reference lmr = 1: level detected was higher than the reference law pcm - law selection law = 0: a-law is selected law = 1: m -law (255 pcm) is selected lin linear mode selection lin = 0: pcm-mode is selected lin = 1: linear mode is selected 2) ptg2 user programmed frequency or fixed frequency is selected ptg2 = 0: fixed frequency for tone generator 2 is selected (1 khz) ptg2 = 1: programmed frequency for tone generator 2 is selected ptg1 user programmed frequency or fixed frequency is selected ptg1 = 0: fixed frequency for tone generator 1 is selected (1 khz) ptg1 = 1: programmed frequency for tone generator 1 is selected 1) explanation of the level metering function: a signal fed to a/-law compression via ax- and hpx-filters (from a digital loop, or externally via vin), is rectified, and the power is measured. if the power exceeds a certain value, loaded to xr4, bit lmr is set to 1. the power of the incoming signal can be adjusted by ax-filters. 2) during linear operation only one 16 bit voice channel, is available per time slot. depending on the address bit (ad) the voice-data of channel 1 or 2 is transmitted. the other voice channel is not available during this time. bit76543210 th-sel lm lmr law lin ptg2 ptg1
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 29 1997-07-01 3.3.3 cr3 configuration register 3 cot/r selection of cut off transmit/receive paths 0 0 0: normal operation 0 0 1: cot_16k cut off transmit path at 16 khz (input of th-filter) 0 1 0: cot_pcm cut off transmit path at 8 khz (input of compression) (output is zero for m -law and linear mode, 1 lsb for a-law) 1 0 1: cor_pfi cut off receive path at 4 mhz (pofi-output) 1 1 0: cor_64k cut off receive path at 64 khz (im-filter input) idr initialize data ram idr = 0: normal operation is selected idr = 1: contents of data ram is set to 0 (used for production test purposes) version the version number shows the actual design version of iom-2-sicofi-2 (100 for peb 2265 v1.1) bit76543210 cot/r 0 idr version
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 30 1997-07-01 figure 8 cut offs and loops
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 31 1997-07-01 3.3.4 cr4 configuration register 4 test-loops 4 bit field for selection of analog and digital loop backs 0 0 0 0: no loop back is selected (normal operation) 0 0 0 1: alb-pfi analog loop back via prefi-pofi is selected 0 0 1 1: alb-4m analog loop back via 4 mhz is selected 0 1 0 0: alb-pcm analog loop back via 8 khz (pcm) is selected 0 1 0 1: alb-8k analog loop back via 8 khz (linear) is selected 1 0 0 0: dlb-ana digital loop back via analog port is selected 1 0 0 1: dlb-4m digital loop back via 4 mhz is selected 1 1 0 0: dlb-128k digital loop back via 128 khz is selected 1 1 0 1: dlb-64k digital loop back via 64 khz is selected 1 1 1 1: dlb-pcm digital loop back via pcm-registers is selected agx analog gain in transmit direction agx = 0: analog gain is disabled agx = 1: analog gain is enabled (6,02db amplification) agr analog gain in receive direction agr = 0: analog gain is disabled agr = 1: analog gain is enabled (6,02db attenuation) d-hpx disable highpass in transmit direction d-hpx = 0: transmit high pass is enabled d-hpx = 1: transmit high pass is disabled 1) d-hpr disable highpass in receive direction d-hpr = 0: receive high pass is enabled d-hpr = 1: receive high pass is disabled 2) 1) in this case the transmit-path signal is attenuated 0.06 db 2) in this case the receive-path signal is attenuated 0.12 db bit76543210 test-loops agx agr d-hpx d-hpr
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 32 1997-07-01 3.4 cop command with a cop command coefficients for the programmable filters can be written to the iom-2 C sicofi-2 coefficient ram or read from the coefficient ram via the iom-2 interface for verification ad address ad = 0 iom-2 C sicofi-2 channel 1 is addressed ad = 1 iom-2 C sicofi-2 channel 2 is addressed rw read/write rw = 0 subsequent data is written to the iom-2 C sicofi-2 rw = 1 read data from iom-2 C sicofi-2 rst reset rst = 1 reset iom-2 C sicofi-2 (same as reset-pin, valid for all two channels) code includes number of following bytes and filter-address bit76543210 ad rw rst 0 code3 code2 code1 code0 0000 th-filter coefficients (part 1) (followed by 8 bytes of data) 0001 th-filter coefficients (part 2) (followed by 8 bytes of data) 0010 th-filter coefficients (part3) (followed by 8 bytes of data) 0100im-filter coefficients (part1) (followed by 8 bytes of data) 0101im-filter coefficients (part2) (followed by 8 bytes of data) 0110 frx-filter coefficients (followed by 8 bytes of data) 0111 frr-filter coefficients (followed by 8 by tes of data) 1000 ax-filter coefficients (followed by 4 bytes of data) 1001 ar-filter coefficie nts (followed by 4 bytes of data) 1100tg 1-filter coefficients (followed by 4 bytes of data) 1101tg 2-filter coefficients (followed by 4 bytes of data)
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 33 1997-07-01 how to program the filter coefficients th-filter: two sets of th-filter coefficients can be loaded to the iom-2 C sicofi-2.each of the two sets can be selected for any of the two iom-2 C sicofi-2 channels, by setting the value of th-sel in configuration register cr2. coefficient set 1 is loaded to the iom-2-sicofi-2 via channel 1, set 2 is loaded via channel 2. ax, ar, im, frx, frr-filter: an individual coefficient set is available for each of the two channels tone-generators: an individual coefficient set is available for each of the two channels an independent set of coefficients is available for all the two channels, for all the filters and tone-generators. two sets of th-filter coefficients can be loaded to the iom-2 C sicofi-2. each of the two sets can be selected for any of the two iom-2 C sicofi-2 channels, by setting the value of th-sel in configuration register cr2. coefficients set #1 is loaded to the iom-2-sicofi-2 via channel 1, set #2 is loaded via channel 2 and so on. note: after reset coefficient set #1 is used for all of the two channels, as all bits in configuration register cr2 are set to 0'. figure 9 channel 2 im part1 filter im part2 filter frx-filter frr-filter ax-filter ar-filter tg1, tg2 channel 1 im part1 filter im part2 filter frx-filter frr-filter ax-filter ar-filter tg1, tg2 th part1 th part2 chan. 1 th part1 th part2 chan. 2 th part1 th part2 chan. 1 channel registers peb 2265, iom2-sicofi? 2 general registers
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 34 1997-07-01 3.5 xop command with the xop command, the iom-2 C sicofi-2 c/i channel in the selected time slot 1) is configured and evaluated. rw read / write information: enables reading from the iom-2 C sicofi-2 or writing information to the iom-2 C sicofi-2 rw = 0 write to iom-2 C sicofi-2 rw = 1 read from iom-2 C sicofi-2 lsel length select information, for setting the number of subsequent data bytes lsel = 000 0 bytes of data are following lsel = 001 1 byte of data is following (xr1) lsel = 010 2 bytes of data are following (xr2, xr1) lsel = 011 3 bytes of data are following (xr3, xr2, xr1) lsel = 100 4 bytes of data are following (xr4, xr3, xr2, xr1) 3.5.1 xr1 extended register 2) sb2_1 status of pin sb2_1 is transferred to the upstream master device sb2_0 status of pin sb2_0 is transferred to the upstream master device si2_0 status of pin si2_0 is transferred to the upstream master device sb1_1 status of pin sb1_1 is transferred to the upstream master device sb1_0 status of pin sb1_0 is transferred to the upstream master device si1_0 status of pin si1 _0 is transferred to the upstream master device 1) iom-2 time slot ts0, ts2, ts4 or ts6, by pin-strapping the pins tss0 and tss1 2) register xr1 can only be read. 1) bits si1_0 and si2_0 have special meaning depending on contents of xr2 (see page 35 ). bit76543210 0 rw 0 1 1 lsel2 lsel1 lsel0 bit76543210 sb2_1 sb2_0 si2_0 1) si2_0 1) sb1_1 sb1_0 si1_0 1) si1_0 1)
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 35 1997-07-01 3.5.2 xr2 extended register 2 register xr2 configures the data-upstream command/indication channel. upstream update interval n to restrict the rate of upstream c/i-bit changes, deglitching (persistence checking) of the status information from the slic may be applied. new status information will be transmitted upstream, after it has been stable for n milliseconds. n is programmable in the range of 1 to 15 ms in steps of 1 ms, with n = 0 the deglitching is disabled. detector select sampling interval t slics with multiplexed loop- and ground-key-status, which have a single status output pin for carrying the loop- and ground-keystatus information, need a special detector select input. lgkm0 is detector select output for channel 1 and 2. bit76543210 nt field n update interval time 0 0 0 0 deglitching is disabled 0 0 0 1 upstream transmission after 1 ms 0 0 1 0 upstream transmission after 2 ms ..... ..... 1 1 1 0 upstream transmission after 14 ms 1 1 1 1 upstream transmission after 15 ms field t time interval t between detector selected high states 0000detector select output lgkm0 is pr ogram. to 0 permanently 0001time inter val t is 1 ms 0010time inter val t is 2 ms ..... ..... 1110time inter val t is 14 ms 1111detector select output lgkm0 is pr ogram. to 1 permanently
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 36 1997-07-01 slics with multiplexed loop / ground key detect figure 10 iom-2 C sicofi-2 pin lgkm0 is a detector select output. this command output pin are normally set to logical 0, such that the slic outputs loop status, which is passed to xr1-bits 0 and 4 via indication pins si1_0 and si2_0. every t milliseconds, the detector select output change to logical 1 for a time of 125 m s (period fsc). during this time the ground key status is read from the slic and transferred upstream using xr1 - bits 1 and 5 via indication pins six_0 and siy_0. the time interval t is programmable from 1 ms to 14 ms in 1ms steps. it is possible to program the output to be permanently logical 0 or 1. slic #1 slic #2 data upstream slic detector select control t programmable t xr1 loop/gnd key input from slic loop/gnd key input from slic sb2_1 iom2-sicofi-2 (channel 1 and 2) sb2_0 si2_0 lgkm0 sb1_1 sb1_0 si1_0 0 1 2 3 4 5 6 7
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 37 1997-07-01 3.5.3 xr3 extended register 3 this register controls the direction of the programmable c/i pins. psb2_1 programmable bi-directional c/i pin sb2_1 is programmed psb2_1 = 0: pin sb2_1 is indication input psb2_1 = 1: pin sb2_1 is command output psb2_0 programmable bi-directional c/i pin sb2_0 is programmed psb2_0 = 0: pin sb2_0 is indication input psb2_0 = 1: pin sb2_0 is command output psb1_1 programmable bi-directional c/i pin sb1_1 is programmed psb1_1 = 0: pin sb1_1 is indication input psb1_1 = 1: pin sb1_1 is command output psb1_0 programmable bi-directional c/i pin sb1_0 is programmed psb1_0 = 0: pin sb1_0 is indication input psb1_0 = 1: pin sb1_0 is command output 3.5.4 xr4 extended register 4 this register holds the offset value for the level metering function. it is only available via the first used time slot. 3.6 slic interface the signaling connection between iom-2 C sicofi-2 and a slic is performed by the iom-2 C sicofi-2 command/indication pins. data received from the downstream c/i byte are inverted and transferred to command output pins (sb, so). data on input pins (si, sb) are inverted and transferred to the upstream c/i-byte. bit76543210 psb2_1 psb2_0 0 0 psb1_1 psb1_0 0 0 bit765432 10 of7 of6 of5 of4 of3 of2 of1 of0
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 38 1997-07-01 3.7 iom ? -2 interface command/indication byte the iom-2 C sicofi-2 offers a 8 pin parallel command/indication slic interface per channel. indication input pins six_0, six_1 six_2 command output pins sox_0, sox_1, sox_2 program. command/indication pins sbx_0, sbx_1 (with x: 1 4) data present at six_0, six_1, six_2 and sbx_0, sbx_1 (if programmed as input) are sampled, inverted and transferred upstream. data received downstream from iom-2-interface are latched, inverted and fed to sox_0, sox_1, sox_2 and sbx_0, sbx_1 (if output). data-downstream c/i channel byte format (receive) the iom-2 channel contains 6 bits (for two voice channels) in both directions for analog devices like the iom-2 C sicofi-2. as the iom-2 C sicofi-2 has up to five command output pins per channel (depending on xr3) it is not possible to send commands to all pins at a time. so c/i-channel bit 5 is used as an address bit to select the channel for the command data on c/i-channel bits 4 0. general case: example for iom-2 C sicofi-2 channels 1 and 2 (iom-2 time slot 0): 1) if sbx_y is programmed as command output. bit543210 ad sbx_1 sbx_0 sox_2 sox_1 sox_0 bit543210 1 sb1_1 1) sb1_0 1) so1_2 so1_1 so1_0 bit543210 0 sb2_1 1) sb2_0 1) so2_2 so2_1 so2_0
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 39 1997-07-01 data upstream c/i channel byte format (transmit) as the c/i-channel holds only 6 bits for two voice channels and the iom-2 C sicofi-2 has up to five indication pins per voice channel, only pins si1_1 and si1_2 for voice channel 1, and pins si2_1 and si2_2 for voice channel 2 are fed directly to the c/i-channel. any change at one of the other indication pins (six_0, sbx_0 and sbx_1) will generate an interrupt per channel, which is transmitted upstream immediately (c/i-channel bits 2 and 5). data on those pins is fed to register xr1 and can be evaluated with a xop-read command. figure 11 itd09991 sb2_1 sb2_0 si2_0 xr1(5,4) xr1(6) xr1(7) int2 c/i5 c/i4 si2_2 c/i3 si2_1 sb2_1 sb2_0 si2_0 si2_2 si2_1 xr1(3) sb1_1 xr1(1,0) xr1(2) sb1_0 si1_0 sb1_1 si1_2 si1_2 int1 c/i2 sb1_0 si1_0 si1_1 c/i1 c/i0 si1_1 "0" on change "0" on change "0" on change "0" on change "0" on change "0" on change r iom -2 - sicofi -2 (2 channels, 1 time-slot) r if an interrupt occurs in one channel, changes in the neighboring channel will also generate an interrupt. channel 2 channel 1
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 40 1997-07-01 figure 12 data flow itd09992 deglitching time sampling of pins (value between is ignored) pin transferred directly via c/i pin transferred via register data on c/i-channel interrupt transferred on c/i dd read-register signal data transferred in register 1212 change 1 change 2 1 22 1 data on signaling pins has to be stable for at least 2 samples, to be transferred du or to trigger an interrupt. during active interrupt data on pins transferred via register is not sampled. after clearing the interrupt, change 2 is detected, which generates a new interrupt.
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 41 1997-07-01 3.8 operating modes figure 13 3.8.1 reset (basic setting mode) upon initial application of v dd or resetting pin reset to 1 during operation, or by software-reset (see cop command), the iom-2 C sicofi-2 enters a basic setting mode. basic setting means, that the iom-2 C sicofi-2 configuration registers cr1q cr4 and xr1 xr3 are initialized to 0 for all channels. all programmable filters are disabled, a-law is chosen, all programmable command/indication pins are inputs. the two tone generators as well as any testmodes are disabled. there is no persistence checking. receive signaling registers are cleared. du-pin is in high impedance state, the analog outputs and the signaling outputs are forced to ground.
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 42 1997-07-01 if any voltage is applied to any input-pin before initial application of v dd , the iom-2 C sicofi-2 may not enter the basic setting mode. in this case it is necessary to reset the iom-2 C sicofi-2 or to initialize the iom-2 C sicofi-2 configuration registers to 0. the iom-2 C sicofi-2 leaves this mode automatically with the beginning of the next 8-khz frame (reset-pin is released). 3.8.2 standby mode after releasing the reset-pin, (reset-state), beginning with the next 8 khz frame, the iom-2 C sicofi-2 will enter the standby mode. the iom-2 C sicofi-2 is forced to standby mode with the pwrup bit set to 0 in the sop command (powerdown). the two channels must be programmed separately. during standby mode the serial iom-2 C sicofi-2 iom-2 interface is ready to receive and transmit commands and data. received voice data on dd-pin will be ignored. iom-2 C sicofi-2 configuration registers and coefficient ram can be loaded and read back in this mode. data downstream c/i-channel data is fed to appropriate command pins. data on indication pins is transmitted data upstream. 3.8.3 operating mode the operating mode for any of the two channels is entered upon recognition of a pwrup bit set to 1 in a sop command for the specific channel. table 6 cr1 cr4 00 h xr1 xr4 00 h coefficient ram not defined command stack cleared dd-input ignored du-output high impedance vout1,2 gnda1,2 sbx_y input sox_y gndd table 7 iom-2 voice channels 11111111 (idle) vout1, 2 gnda1, 2
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 43 1997-07-01 3.9 programmable filters based on an advanced digital filter concept, the peb 2265 provides excellent transmission performance and high flexibility. the new filter concept leads to a maximum independence between the different filter blocks. 3.9.1 impedance matching filter ? realization by 3 different loops C 4 mhz: multiplication by a constant (12 bit) C 128 khz: wave digital filter (iir) (60 bit) improves low frequency response) C 64 khz: fir-filter (48 bit) (for fine-tuning) ? improved stability behavior of feedback loops ? real part of termination impedance positive under all conditions ? improved overflow performance for transients ? return loss better 30 db 3.9.2 transhybrid balancing (th) filter ? new concept: 2 loops at 16 khz ? flexible realization allows optimization of wide impedance range ? consists of a fixed and a programmable part C 2nd order wave digital filter (iir) (106 bit) (improves low frequency response) C 7-tap fir-filter (84 bit) (for fine-tuning) ? trans-hybrid-loss better 30 db (typically better 40 db, device only) ? adaptation to different lines by: C easy selection between two different d ownloaded coefficient sets 3.9.3 filters for frequency response correction ? for line equalization and compensation of attenuation distortion ? improvement of group-delay-distortion by using minimum phase filters (instead of linear phase filters) ? frr filter for correction of receive path distortion C 5 tap programmable fir filter operating at 8 khz (60 bit) ? frx filter for correction of transmit path distortion C 5 tap programmable fir filter operating at 8 khz (60 bit) ? frequency response better 0.1 db
peb 2265 programming the iom ? -2 C sicofi ? -2 semiconductor group 44 1997-07-01 3.9.4 amplification/attenuation -filters ax1, ax2, ar1, ar2 ? improved level adjustment for transmit and receive ? two separate filters at each direction for C improved trans-hybrid balancing C optimal adjustment of digital dynamic range C gain adjustments independent of th-filter 3.9.5 amplification/attenuation receive (ar1, ar2)-filter step size for ar-filter range 3 - 14 db: step size 0.02 0.05 db range - 14 - 24 db:step size 0.5 db 3.9.6 amplification/attenuation transmit (ax1, ax2)-filter step size for ax-filter range - 3 14 db: step size 0.02 0.05 db range 14 24 db: step size 0.5 db
peb 2265 qsicos software semiconductor group 45 1997-07-01 4 qsicos software the qsicos-software has been developed to help to obtain an optimized set of coefficients both quickly and easily. the qsicos program runs on any pc with at least 575 kbytes of memory. this also requires ms-dos version 5.0 or higher, as well as extended memory. figure 14 4.1 qsicos supports ? calculation of coefficients for the C impedance filter (im) for return loss calculation C frr and frx-filters for frequency response in receive and transmit path C ar1, ar2 and ax1, ax2-filter for level adjustment in receive and transmit path C trans-hybrid balancing filter (th) and C two programmable tone generators (tg 1 and tg 2) ? simulation of the peb 2265 and slic system with fixed filter coefficients allows simulations of tolerances which may be caused e.g. by discrete external components. ? graphical output of transfer functions to the screen for C return loss C frequency responses in receive and transmit path C transhybrid loss ? calculation of the peb 2265 and slic system stability . the im-filter of the peb 2265 adjust the total system impedance by making a feedback loop. because the line is also a part of the total system, a very robust method has to used to avoid oscillations and to ensure system stability. the input impedance of the peb 2265 and slic combination is calculated. if the real part of the system input impedance is positive, the total system stability can be guaranteed. k-parameter interface- file country-spec sicofi coefficients file automatic k-param extraction line interface line interface line interface line interface k11=(zin-zg)/(zin+zg) k12=2*v1/v3 k21=v2/vg k22=v2/v3 software for filter-coefficients-optimization rd/db f/ hz qsicos simulation (pspice) calculation-controlfile
peb 2265 transmission characteristics semiconductor group 46 1997-07-01 5 transmission characteristics the proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) needs a complete knowledge of the iom-2 C sicofi-2s analog environment, and it is suggested to use the qsicos-program for calculating the propriate coefficients. unless otherwise stated, the transmission characteristics are guaranteed within the test conditions. test conditions t a =0 c to 70 c; v dd =5v 5 %; gnda1 4 = gndd = 0 v r l 1) ) >20k w ; c l < 20 pf; h(im) = h(th) = 0; h(r1) = h(frx) = h(frr) = 1; hpr and hpx enabled; ar 2) = ar1 + ar2 = 0 to C 13 db for sine-wave-, and 0 to C 11 db for ccitt-noise-measurements ax 3) = ax1 + ax2 = 0 to 13 db for sine-wave-, and 0 to 11 db for ccitt-noise-measurements f = 1014 hz; 0 dbm0; a-law or m -law; agx = 0 db, 6.02 db, agr = 0 db, - 6.02 db; in transmit direction for m -law an additional gain of 1.94 db is implemented automatically, in the companding block (cmp). this additional gain has to be considered at all gain calculations, and reduces possible ax-gain. a 0dbm0 4 4) ) signal is equivalent to 1.095 [1.0906] vrms. a +3.14 [3.17] dbm0 signal is equivalent to 1.57 vrms which corresponds to the overload point of 2.223 v (a-law,[ m -law]). when the gain in the receive path is set at 0 db, an 1014 hz pcm sinewave input with a level 0dbm0 will correspond to a voltage of 1.095 vrms at a-law (1,0906 v m -law) at the analog output. when the gain in the transmit path is set at 0 db, an 1014hz sine wave signal with a voltage of 1.095 vrms a-law (1.0906 v m -law) will cor respond to a level of 0 dbm0 at the pcm output. 1) r l , c l forms the load on vout 2) consider, in a complete system, ar=ar1+ar2+frr+r1= 0 to - 13 db ( - 11 db for ccitt-noise-measurement) 3) consider, in a complete system, ax = ax1 + ax2 + frx = 0 to 13 db (11 db for ccitt-noise-measurement) for a-law, 0 to 11 db (9 db for ccitt-noise-measurement) for m -law 4) the absolute power level in decibels referred to the pcm interface levels.
peb 2265 transmission characteristics semiconductor group 47 1997-07-01 1) using equal-level, 4-tone method (eia) at a composite level of - 13 dbm0 with frequencies in the range between 300 hz and 3400 hz. table 8 parameter symbol limit values unit min typ. max. gain absolute (agx = agr = 0) t a =25 c; v dd =5v t a =0 - 70 c; v dd =5v 5% g C 0.15 C 0.25 0.10 + 0. 15 +0.25 db db gain absolute (agx = 6.02 db, agr = - 6.02 db) t a =25 c; v dd =5v t a =0 - 70 c; v dd =5v 5% C 0.15 C 0.25 0.10 + 0. 15 +0.25 db db harmonic distortion, 0 dbm0; f = 1000 hz; 2 nd ,3 rd order hd C50 C44 db intermodulation 1) r 2 r 3 imd imd C46 C56 db db crosstalk 0 dbm0; f = 200 hz to 3400 hz any combination of direction and channel ct C85 C80 db idle channel noise, transmit, a-law, psophometric v in =0v transmit, m -law, c-message v in =0v receive, a-law, psophometric idle code + 0 receive, m -law, c-message idle code + 0 n tp n tc n rp n rc C85 5 C 67.4 17.5 C 78.0 12.0 dbm0p dbmc dbm0p dbmc
peb 2265 transmission characteristics semiconductor group 48 1997-07-01 5.1 frequency response 5.1.1 receive: reference frequency 1 khz, input signal level 0 dbm0 figure 15 5.1.2 transmit: reference frequency 1 khz, input signal level 0 dbm0 figure 16 itd10002 0 -1 khz f 0 1 2 attenuation db 1 2 3 3.4 0.125 -0.125 0.65 0.2 0.3 3.2 hpr is off db db db itd10001 0 -1 khz f 0 1 2 attenuation db 1 2 3 3.4 0.2 3.2 0.1 0.3 -0.125 0.125 0.65 db db db
peb 2265 transmission characteristics semiconductor group 49 1997-07-01 5.2 group delay maximum delays when the iom-2 C sicofi-2 is operating with h(th) = h(im) = 0 and h(frr) = h(frx) = 1 including delay through a/d- and d/a converters. specific filter programming may cause additional group delays. group delay deviations stay within the limits in the figures below. 5.2.1 group delay absolute values: input signal level 0 dbm0 5.2.2 group delay distortion transmit: input signal level 0 dbm0 figure 17 table 9 parameter symbol limit values unit reference min. typ. max. transmit delay d xa 300 m s receive delay d ra 250 m s itd09999 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 200 300 400 500 s khz t f 150 d g 0.6 85 2.6 2.8 m
peb 2265 transmission characteristics semiconductor group 50 1997-07-01 5.2.3 group delay distortion receive: input signal level 0dbm0 1) . figure 18 5.3 out-of-band signals at analog input with an 0 dbm0 out-of-band sine wave signal with frequency f (<<100 hz or 3,4 khz to 100 khz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least x db below a 0 dbm0, 1 khz sine wave reference signal at the analog input. 2) 1) hpr is switched on: reference point is at t gmin hpr is switched off: reference point is at 1.5 khz 2) poles at 12 khz 150 hz and 16 khz 150 hz are be provided itd09999 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 200 300 400 500 s khz t f 150 d g 0.6 85 2.6 2.8 m
peb 2265 transmission characteristics semiconductor group 51 1997-07-01 figure 19 3.4 4.0 khz: 4.0 4.6 khz: 5.4 out-of-band signals at analog output with a 0 dbm0 sine wave with frequency f (300 hz to 3.99 khz) applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least x db below a 0 dbm0, 1 khz sine wave reference signal at the analog output. figure 20 3.4 4.6 khz: 0 0 khz f 100 0.06 0.1 3.4 4 4.6 6 10 18 10 20 30 40 db transmit out of band discrimination x 25 35 32 15 itd09998 x14 p 4000 f C 1200 ---------------------- - ? ?? sin 1 C ? ?? C = x18 p 4000 f C 1200 ---------------------- - ? ?? sin 7 9 -- - C ? ?? C = 0 0 khz f 100 0.06 0.1 3.4 4 4.6 6 10 18 db receive out of band discrimination x 10 20 30 40 50 60 15 35 10.55 8 16 28 57 itd09997 x14 p 4000 f C 1200 ---------------------- - ? ?? sin 1 C ? ?? C =
peb 2265 transmission characteristics semiconductor group 52 1997-07-01 5.5 out of band idle channel noise at analog output with an idle code applied to the digital input, the level of any resulting out-of-band power spectral density (measured with 3 khz bandwidth) at the analog output, will be not greater than the limit curve shown in the figure below. figure 21 5.6 overload compression m -law, transmit: measured with sine wave f = 1014 hz. figure 22 -100 f 10 12 10 3 10 4 10 khz -90 -80 -70 -60 -50 -40 dbm0 -55 -78 sicofi -4 r itd09996 0 fundamental input power -1 fundamental 0 1 2 3 4 5 6 7 8 dbm0 10 0.25 -0.25 1 2 3 4 5 6 7 dbm0 9 output power itd09995
peb 2265 transmission characteristics semiconductor group 53 1997-07-01 5.7 gain tracking (receive or transmit) the gain deviations stay within the limits in the figures below gain tracking: (measured with sine wave f = 1014 hz, reference level is 0 dbm0) figure 23 5.8 total distortion the signal to distortion ratio exceeds the limits in the fol lowing figure. 5.8.1 total distortion measured with sine wave receive or transmit: measured with sine wave f = 1014 hz. (c-message weighted for m -law, psophometricaly weighted for a-law) figure 24 itd09994 -70 -2 -1 0 1 2 db -1.4 -0.5 -0.25 0.25 0.5 1.4 d g input level -55 -37 -60 -50 -40 -30 -20 -10 0 10 dbm0 3
peb 2265 transmission characteristics semiconductor group 54 1997-07-01 5.8.2 total distortion measured with noise according to ccitt receive figure 25 transmit figure 26
peb 2265 transmission characteristics semiconductor group 55 1997-07-01 5.9 single frequency distortion an input signal with its frequency swept between 0.3 to 3 khz for the receive path, or 0 to 12 khz for the transmit path, any generated output signal with other frequency than the input frequency will stay 28 db below the maximum input level of 0 dbm0. 5.10 transhybrid loss the quality of transhybrid-balancing is very sensitive to deviations in gain and group delay - deviations inherent to the iom-2 C sicofi-2 a/d- and d/a-converters as well as to all external components used on a line card (slic, op s etc.) measurement of iom-2 C sicofi-2 transhybrid-loss: a 0 dbm0 sine wave signal and a frequency in the range between 300 - 3400 hz is applied to the digital input. the resulting analog output signal at pin v out is directly connected to v in , e.g. with the iom-2 C sicofi-2 testmode digital loop back via analog port. the programmable filters frr, ar, frx, ax and im are disabled, the balancing filter th is enabled with coefficients optimized for this configuration ( v out = v in ). the resulting echo measured at the digital output is at least x db below the level of the digital input signal as shown in the table below (filter coefficients will be provided). the listed values for thl correspond to a typical variation of the signal amplitude and -delay in the analog blocks. d amplitude = typ. 0.15 db d delay = typ. 0.5 m s table 10 receive transmit frequency max. input level frequency max. input level 300 hz to 3.4 khz 0 dbm0 0 to 12 khz 0 dbm0 table 11 parameter symbol limit values unit test condition min. typ. trans hybrid loss at 300 hz thl 300 27 40 db t a =25 c; v dd =5v trans hybrid loss at 500 hz thl 500 33 45 db t a =25 c; v dd =5v trans hybrid loss at 2500 hz thl 2500 29 40 db t a =25 c; v dd =5v trans hybrid loss at 3000 hz thl 3000 27 35 db t a =25 c; v dd =5v trans hybrid loss at 3400 hz thl 3400 27 35 db t a =25 c; v dd =5v
peb 2265 electrical characteristics semiconductor group 56 1997-07-01 6 electrical characteristics 6.1 absolute maximum ratings table 12 parameter symbol limit values unit test condition min. max. v dd referred to gndd - 0.3 7.0 v gnda to gndd - 0.6 0.6 v analog input and output voltage referred to v dd =5v; referred to gnda = 0 v - 5.3 - 0.3 0.3 5.3 v v all digital input voltages referred to gndd = 0 v; ( v dd =5v) referred to v dd =5v; (gndd = 0 v) - 0.3 - 5.3 5.3 0.3 v v dc input and output current at any input or output pin (free from latch -up) 10 ma storage temperature t stg - 60 125 c ambient temperature under bias t a - 10 80 c power dissipation (package) p d 1w
peb 2265 electrical characteristics semiconductor group 57 1997-07-01 6.2 operating range t a = 0 to 70 c; v dd =5v 5 %; gndd = 0 v; gnda = 0 v 6.3 digital interface t a = 0 to 70 c; v dd =5v 5%; gndd=0v; gnda=0v all input-pins, with exception of the reset-pin, have a ttl-input characteristic. table 13 parameter symbol limit values unit test condition min. typ. max. v dd supply current standby operating (2 channels) i dd 1.2 27 2 40 ma ma power supply rejection of either supply/direction receive v dd guaranteed receive v dd target value psrr 30 14 30 db db db ripple: 0 to 150 khz, 70 mvrms measured: 300 hz to 3.4 khz measured: at f : 3.4 to 150 khz power dissipation standby pd s 15 20 mw power dissipation operating pd o1 75 110 mw 1 channel operating power dissipation operating pd o2 100 140 mw 2 channels operating table 14 parameter symbol limit values unit test condition min. max. low-input voltage v il - 0.3 0.8 v high-input voltage v ih 2.0 v low-output voltage v ol 0.45 v i o = - 5ma low-output voltage du pin v ol 0.45 v i o = - 7ma, r l =1k w high-output voltage v oh 4.4 v i 0 = 5 ma input leakage current i il 1 m a - 0.3 v in v dd
peb 2265 electrical characteristics semiconductor group 58 1997-07-01 6.4 analog interface t a = 0 to 70 c; v dd =5v 5 %; gndd = 0 v; gnda = 0 v 6.5 reset timing to reset the iom-2 C sicofi-2 to basic setting mode, positive pulses applied to pin rs have to be higher than 2.4 v (cmos-schmitt-trigger input) and longer than 3 m s. signals shorter than 1 m s will be ignored. table 15 parameter symbol limit values unit test condition min. typ. max. analog input resistance r i 160 270 480 k w analog output resistance r o 10 w analog output load r l c l 20 20 k w pf input leakage current i il 0.1 1.0 m a0 v in v dd input voltage range (ac) v ir 2.223. v
peb 2265 electrical characteristics semiconductor group 59 1997-07-01 6.6 iom ? -2 interface timing 6.6.1 4-mhz operation mode (mode = 1) figure 27 switching characteristics table 16 parameter symbol limit values unit min. typ. max. period dcl fast mode 1) t dcl 1/4096 khz dcl duty cycle 40 60 % period fsc 1) t fsc 125 m s fsc setup time t fsc_s 70 t dclh ns fsc hold time t fsc_h 40 ns dd data in setup time t dd_s 20 ns dd data in hold time t dd_h 50 ns du data out delay 2) t ddu 150 320 ns 1) dcl = 4096 khz: t fsc = 512 t dcl 2) depending on pull-up resistor used in application (typical 1 k w ), du is a open drain - line itd03389 t dcl t dclh t fsc_s t fsc_h t fsc tt dd_h t ddu t dduhz dd_s high imp. dcl fsc dd du 10% 90%
peb 2265 electrical characteristics semiconductor group 60 1997-07-01 6.6.2 2-mhz operation mode (mode = 0) figure 28 switching characteristics table 17 parameter symbol limit values unit min. typ. max. period dcl slow mode 1) t dcl 1/2048 khz dcl duty cycle 40 60 % period fsc 1) t fsc 125 m s fsc setup time t fsc_s 70 t dclh ns fsc hold time t fsc_h 40 ns dd data in setup time t dd_s 20 ns dd data in hold time t dd_h 50 ns du data out delay 2) t ddu 150 175 ns 1) dcl = 2048 khz: t fsc = 256 t dcl 2) depending on pull up resistor used in application (typical 1 k w ), du is a open drain - line. itd09993 t dcl dcl fsc dd du fsc_s t dclh t high imp. t dd_s dd_h t t ddu dduhz t t fsc_h fsc t
peb 2265 electrical characteristics semiconductor group 61 1997-07-01 6.7 iom ? -2 command/indication interface timing 6.7.1 4-mhz operation mode (mode = 1) figure 29
peb 2265 electrical characteristics semiconductor group 62 1997-07-01 6.7.2 2-mhz operation mode (mode = 0) figure 30 switching characteristics table 18 parameter symbol limit values unit min. typ. max. command out delay t dcout 150 250 ns command out high impedance t dcz 150 250 ns command out active t dca 150 250 ns indication in setup time t lin_s 50 ns indication in hold time t lin_h 100 ns
peb 2265 electrical characteristics semiconductor group 63 1997-07-01 6.8 detector select timing figure 31 6.8.1 switching characteristics table 19 parameter symbol limit values unit min. typ. max. detector select high time t lgkmh 125 m s detector select repeat t lgkm 1 14 ms indication in setup time t lin_s 50 ns indication in hold time t lin_h 100 ns
peb 2265 appendix semiconductor group 64 1997-07-01 7 appendix 7.1 iom ? -2 interface monitor transfer protocol 7.1.1 monitor channel operation the monitor channel is used for the transfer of maintenance information between two functional blocks. using two monitor control bits (mr and mx) per direction, the data are transferred in a complete handshake procedure. the mr and mx bits in the fourth octet (c/i channel) of the iom-2 frame are used for the handshake procedure of the monitor channel. the monitor channel transmission operates on a pseudo-asynchronous basis: C data transfer (bits) on the bus is synchronized to frame sync fsc C data flow (bytes) are asynchronously controlled by the handshake procedure. for example: data is placed onto the dd-monitor-channel by the monitor-transmitter of the master device (dd-mx-bit is activated i.e. set to 0). this data transfer will be repeated within each frame (125 m s rate) until it is acknowledged by the iom-2 C sicofi-2 monitor-receiver by setting the du-mr-bit to 0, which is checked by the monitor-transmitter of the master device. thus, the data rate is not 8 kbyte/s. figure 32
peb 2265 appendix semiconductor group 65 1997-07-01 7.1.2 monitor handshake procedure the monitor channel works in 3 states C idle state: a pair of inactive (set to 1) mr- and mx-bits during two or more consecutive frames: end of message (eom) C sending state: mx-bit is activated (set to 0) by the monitor-transmitter, together with data-bytes (can be changed) on the monitor-channel C acknowledging: mr-bit is set to active (set to 0) by the monitor-receiver, together with a data-byte rem aining in the monitor-channel. a start of transmission is initiated by a monitor-transmitter in sending out an active mx-bit together with the first byte of data (the address of the receiver) to be transmitted in the monitor-channel. this state remains until the addressed monitor-receiver acknowledges the received data by sending out an active mr-bit, which means that the data-transmission is repeated each 125 m s frame (minimum is one repetition). during this time the monitor-transmitter evaluates the mr-bit. flow control, means in the form of transmission delay, can only take place when the transmitters mx and the receivers mr bit are in active state. since the receiver is able to receive the monitor data at least twice (in two consecutive frames), it is able to check for data errors. if two different bytes are received the receiver will wait for the receipt of two identical successive bytes (last look function). a collision resolution mechanism (check if another device is trying to send data during the same time) is implemented in the transmitter. this is done by looking for the inactive (1) phase of the mx-bit and making a per bit collision check on the transmitted monitor data (check if transmitted 1s are on du/dd-line; du/dd-line are open-drain lines). any abort leads to a reset of the iom-2 C sicofi-2 command stack, the device is ready to receive new commands. to obtain a maximum speed data transfer, the transmitter anticipates the falling edge of the receivers acknowledgment. due to the inherent programming structure, duplex operation is not possible. it is not allowed to send any data to the iom-2 C sicofi-2, while transmission is active.
peb 2265 appendix semiconductor group 66 1997-07-01 7.1.3 state diagram of the iom ? -2 C sicofi ? -2 monitor transmitter figure 33 mr mr - bit received on dd - line mx mx - bit calculated and expected on du - line mxr mx - bit sampled on du - line cls collision within the monitor data byte on du - line rqt request for transmission form internal source abt abort request/indication . logical and + logical or itd02458 idle mx = 1 mx = 0 1st byte mx = 1 nth byte ack mx = 0 wait for ack wait mx = 1 mx = 1 abort eom mx = 1 mr mr mr mr initial state cls/abt any state rqt . . rqt mr . rqt mr mr rqt . . rqt mr mr + mxr mxr mr mxr . . mxr mr mr
peb 2265 appendix semiconductor group 67 1997-07-01 7.1.4 state diagram of the iom ? -2 C sicofi ? -2 monitor receiver figure 34 mr mr - bit calculated and transmitted on du - line mx mx - bit received data downstream (dd - line) ll last lock of monitor byte received on dd - line abt abort indication to internal source . logical and + logical or itd02459 idle mr = 1 mr = 0 1st byte rec new byte mr = 1 abort byte valid mx mx mx mx mx initial state mr = 0 wait for ll mx mx mx mx mx abt any state nth byte rec ll . . ll mx . ll mx mx ll . . ll mx . ll mx mr = 1 wait for ll mr = 0 mr = 0 mr = 1
peb 2265 appendix semiconductor group 68 1997-07-01 7.2 monitor channel data structure the monitor channel is used for the transfer of maintenance information between two functional blocks. by use of two monitor control bits (mr and mx) per direction, the data are transferred in a complete handshake procedure. 7.2.1 address byte messages to and from the iom-2 C sicofi-2 are started with the following monitor byte: thus providing information for two voice channels, the iom-2 C sicofi-2 is one device on one iom-2 time slot. monitor data for a specific voice channel is selected by the iom-2 C sicofi-2 specific command (sop or cop). 7.2.2 identification command in order to be able to unambiguously identify different devices by software, a two byte identification command is defined for analog lines iom-2 devices. each device will then respond with its specific identification code. for the iom-2 C sicofi-2 this two byte identification code is: each byte is transferred at least twice (in two consecutive frames). bit76543210 10000001 10000000 00000000 10000000 10000010
peb 2265 appendix semiconductor group 69 1997-07-01 7.3 iom ? -2 interface programming procedure example for a typical iom-2 interface programming procedure, consisting of identification request and answer, a sop write command with three byte following, and sop read to verify the programming. table 20 frame data down data up monitor mr/mx monitor mr/mx 1 11111111 11 11111111 11 2 idrqt. 1 st byte 10 11111111 11 3 idrqt. 1 st byte 10 11111111 01 4 idrqt. 2 nd byte 11 11111111 01 5 idrqt. 2 nd byte 10 11111111 11 6 11111111 11 11111111 01 7 11111111 11 idans. 1 st byte 10 8 11111111 01 idans. 1 st byte 10 9 11111111 01 idans. 2 nd byte 11 10 11111111 11 idans. 2 nd byte 10 11 11111111 01 11111111 11 12 address 10 11111111 11 13 address 10 11111111 01 14 sop write 11 11111111 01 15 sop write 10 11111111 11 16 cr3 11 11111111 01 17 cr3 10 11111111 11 18 cr2 11 11111111 01 19 cr2 10 11111111 11 20 cr1 11 11111111 01 21 cr1 10 11111111 11 22 sop read 11 11111111 01 23 sop read 10 11111111 11 24 11111111 11 11111111 01 25 11111111 11 address 10
peb 2265 appendix semiconductor group 70 1997-07-01 idrqt identification request (80 h , 00 h ) idans answer to identification request (80 h , 82 h ) address iom-2 C sicofi-2 specific address byte (81 h ) crx data for/from configuration register x. 26 11111111 01 address 10 27 11111111 01 cr3 11 28 11111111 11 cr3 10 29 11111111 01 cr2 11 30 11111111 11 cr2 10 31 11111111 01 cr1 11 32 11111111 11 cr1 10 33 11111111 01 11111111 11 table 20 (contd) frame data down data up monitor mr/mx monitor mr/mx
peb 2265 test features semiconductor group 71 1997-07-01 8 test features 8.1 boundary scan 8.1.1 general the iom-2 C sicofi-2 provides fully ieee std. 1149.1 compatible boundary scan support consisting of: C a complete boundary scan (digital pins) C a test access port controller (tap) C four dedicated pins (tck, tms, tdi, tdo) C a 32 bit icode register all iom-2 C sicofi-2 digital pins expect power supply v dd d and ground gndd are included in the boundary scan. depending on the pin functionality one, two or three boundary cells are provided. when the tap controller is in the appropriate mode, data is shifted into/out of the boundary scan via the pins tdi/tdo controlled by the clock applied to pin tck. the iom-2 C sicofi-2 pins are included in the following sequence in the boundary scan: table 21 pin type number of boundary scan cells usage input 1 input output 2 output, enable i/o 3 input, output, enable table 22 pin number pin name type 57 mode i 59 tss1 i 60 tss0 i 61 n.u.i. i 62 n.u.i. i 63 n.u.i. i 64 n.u.io. i/o 1 n.u.io. i/o
peb 2265 test features semiconductor group 72 1997-07-01 2 n.c. o 3 n.c. o 4 n.c. o 13 n.c. o 14 n.c. o 15 n.c. o 16 n.u.io. i/o 17 n.u.io. i/o 18 n.u.i. i 19 n.u.i. i 20 n.u.i. i 21 n.c. o 22 reset i 24 dd i 25 du o (open drain) 26 dcl i 27 fsc i 28 lgkm0 o 29 si1_2 i 30 si1_1 i 31 si1_0 i 32 sb1_1 i/o 33 sb1_0 i/o 34 so1_2 o 35 so1_1 o 36 so1_0 o 45 so2_0 o 46 so2_1 o 47 so2_2 o 48 sb2_0 i/o table 22 (contd) pin number pin name type
peb 2265 test features semiconductor group 73 1997-07-01 8.1.2 the tap-controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee std. 1149.1. transitions on pin tms (test mode select) cause the tap controller to perform a state change. according to the standard definition five instructions are executable: figure 35 49 sb2_1 i/o 50 si2_0 i 51 si2_1 i 52 si2_0 i table 22 (contd) pin number pin name type
peb 2265 test features semiconductor group 74 1997-07-01 extest is used to examine the board interconnections. intest supports internal chip testing (is the default value of the instruction register) sample/preload provides a snap-shot of the pin level during normal operation, or is used to preload the boundary scan with a test vector icode the 32 bit identification register is serially read out via tdo. it contains a version number (4 bit), a device code (16 bit) and the manufacture code (11 bit). the lsb is fixed to 1. for the iom-2 C sicofi-2 v1.1 the code is: 0011 0000 0000 0001 0101 0000 1000 001 1 tap_test1 39 bit field for selecting operation (level metering offset, loops, tone generator ) tap_test2 wait for level metering result ready (should be > t.b.d. ms) tap_test5 level metering data output (1 bit result of level metering per channel) tap_test4 level metering operation is switched off bypass a bit entering tdi is shifted to tdo after one tck clock cycle table 23 code instruction function 0000 extest external testing 0001 intest internal testing 0010 sample/preload snap-shot testing 0011 icode reading id code 0100 tap_test 1 configuration for level metering 0101 tap_test 2 wait for result 1000 tap_test 5 serial testdata output (level metering results) 0111 tap_test 4 switch off test 11xx bypass bypass operation
peb 2265 test features semiconductor group 75 1997-07-01 8.2 level metering function the level metering function is a functional selftest (available per channel), which allows selftest of the chip (digital, or digital and analogue), and also selftest of the board (including the slic). an external or internally generated sine-wave signal is fed to the receive path. after switching a loop (internal or external via the slic) to the transmit-path the return level is measured and compared to a programmable offset value. the result of this operation (greater or smaller than offset) can be read out via the iom-2 interface (bit lmr in configuration register cr2). there is a single-8-bit offset-register available for both two channels. this offset register can be accessed as xr4 with a xop-command (field lsel = 100) this register contains the 2s complement offset value for the level metering function block diagram figure 36 (for further information, an application note describing the calculation of the offset value and the sensitivity, is available). bit76543210 of7 of6 of5 of4 of3 of2 of1 of0 + im2* agx adc dsi ds2 ax2* frx* ax1* hpx cmp pcmin pcmout lmr sign x offset config.register tg1,2 *programmable transmit path receive path abs a - b im1* th* vin vout agr us2 dac r1* us1 ar2* frr* ar1* hpr* exp lm iom36.wmf
peb 2265 test features semiconductor group 76 1997-07-01 8.3 programming the iom ? -2 C sicofi ? -2 tone generators two independent tone generators are available per channel. when one or both tone-generators are switched on, the voice signal is switched off automatically for the selected voice channel. to make the generated signal sufficient for dtmf, a programmable bandpass-filter is included. the default frequency for both tone generators is 1000 hz. the qsicos-program contains a program for generating coefficients for variable frequencies. byte sequences for programming both the tone generators and the bandpass-filters: the resulting signal amplitude can be set by transmitting the ar1 and ar2 filters. by switching a digital loop the generated sine-wave signal can be fed to the transmit path. 1) 0c is used for programming tone generator 1, in channel 1. 0d is used for programming tone generator 2, in channel 1. table 24 frequency command byte 1 byte 2 byte 3 byte 4 697 hz 0c/0d 1) 0a 33 5a 2c 770 hz 0c/0d 1) 12 33 5a c3 852 hz 0c/0d 1) 13 3c 5b 32 941 hz 0c/0d 1) 1d 1b 5c cc 1209 hz 0c/0d 1) 32 32 52 b3 1336 hz 0c/0d 1) ec 1d 52 22 1477 hz 0c/0d 1) aa ac 51 d2 800 hz 0c/0d 1) 12 d6 5a c0 950 hz 0c/0d 1) 1c f0 5c c0 1008 hz 0c/0d 1) 1a ae 57 70 2000 hz 0c/0d 1) 00 80 50 09
peb 2265 package outlines semiconductor group 77 1997-07-01 9 package outlines gpm05250 p-mqfp-64-1-2 (smd) (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device

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